Search - digital clock verilog code

[VHDL-FPGA-Verilog] Verilog_Development_Board_Sources

Description: 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟-friends, I Jawen. previously seen on the set of CPLD Development Board VHDL source code quite welcome, Now she will also be Verilog source contribution to everyone : eight priority encoder, multipliers, Multi-channel selector, binary to BCD, adder, subtraction device, the simple state machine, four comparators, 7 of the digital control, i2c bus, lcd LCD allocated code switches, serial port, the buzzer sounded, matrix keyboards, Bomadeng. Traffic lights, digital clock
Platform: | Size: 3151872 | Author: Jawen | Hits:

[MPI] clock

Description: 用Verilog HDL写的数字时钟,已经在开发板上验证过的,绝对原创,使用数码管进行显示!-Written using Verilog HDL Digital Clock, has been verified in the development of on-board absolute originality, the use of digital tube display!
Platform: | Size: 2048 | Author: 吴俊泉 | Hits:

[VHDL-FPGA-Verilog] clock_design

Description: 数字钟的verilog代码，quartusII开发环境.-Digital Clock in Verilog code, quartusII development environment.
Platform: | Size: 414720 | Author: 屈开 | Hits:

[VHDL-FPGA-Verilog] multifunction_digital_clock_based_on_fpga

Description: 基于FPGA的多功能数字钟的设计与实现内附有详尽的Verilog HDL源码，其功能主要有：时间设置，时间显示，跑表，分频，日期设置，日期显示等-FPGA-based multi-functional Digital Clock Design and Implementation of typhoons and rainstorms are detailed Verilog HDL source code, its functions include: time settings, time display, stopwatch, frequency, date setting, date display
Platform: | Size: 3293184 | Author: | Hits:

[VHDL-FPGA-Verilog] multifunction_clock

Description: 此为多功能数字电子钟的vhdl代码，有闹钟、时间可调、计时等功能-This is a multi-function digital electronic clock VHDL code, has an alarm clock, time adjustable, timing and other functions
Platform: | Size: 4096 | Author: naturexu | Hits:

[VHDL-FPGA-Verilog] dpll

Description: dpll的verilog代码，完成数字锁相。用于时钟对准，位同步。-dpll the verilog code to complete the digital phase-locked. Alignment for the clock, bit synchronization.
Platform: | Size: 1024 | Author: hsj | Hits:

[VHDL-FPGA-Verilog] clock

Description: 多功能数字钟Verilog HDL的源码，能够整点报时，报整点数，设定任意时刻闹钟，低音高音两种频率。-Multi-function digital clock Verilog HDL source code, set the alarm clock at any time, bass treble two frequencies. It s for FPGA.
Platform: | Size: 984064 | Author: Stone Lei | Hits:

[VHDL-FPGA-Verilog] clock

Description: verilog hdl代码实现显示在数码管上显示时间，日期-verilog hdl code to achieve control in the digital display shows time, date. .
Platform: | Size: 2048 | Author: Along | Hits:

[VHDL-FPGA-Verilog] digital-clock-

Description: 本代码采用verilog HDL语言编写。实现的是数字跑表计时功能-The code using verilog HDL language. Implementation is a digital stopwatch timer functions
Platform: | Size: 161792 | Author: 西蟀 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 数显时钟编码，verilog 代码实现，其中含有测试文件-Digital clock code, verilog code, which contains the test file
Platform: | Size: 1024 | Author: 张恒 | Hits:

[VHDL-FPGA-Verilog] Multifunction-digital-clock

Description: 这是多功能数字钟的Verilog源程序，此程序已经编译通过，可以使用-This is a multi-functional digital clock in Verilog source code, this program has been compiled by, you can use
Platform: | Size: 493568 | Author: 莫然 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 数字时钟的Verilog代码，该实验经本人测试，正确无误。-Digital clock Verilog code, the experiment after my test, correct.
Platform: | Size: 5120 | Author: 杜云 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 一个简单的数字时钟Verilog仿真程序，60秒1分钟，60分一小时，24小时一天，265天一年。代码逻辑简化不含状态机，易理解。附激励文件可直接仿真。-A simple digital clock Verilog simulation program 60 seconds, 1 minute, 60 hours, 24 hours a day, 265 days a year. The code logic simplifies excluding state machine, easy to understand.
Platform: | Size: 1024 | Author: Welson | Hits:

[VHDL-FPGA-Verilog] digital-timer

Description: 数字时钟的verilog代码，以仿真编译通过，可直接用-Digital clock verilog code which is compiled and simulated and can be directly used
Platform: | Size: 167936 | Author: 谢文斌 | Hits:

[VHDL-FPGA-Verilog] muti-function-clock

Description: 用来实现多功能数字钟，可调节闹钟铃声和数码管显示-muti-function digital clock verilog code
Platform: | Size: 2048 | Author: 徐以为 | Hits:

[VHDL-FPGA-Verilog] shuzishizhong

Description: 这是基于verilog hdl的数字时钟源代码，能够实现时分秒的计时，可以手动进行调时与调分。-This is based on the digital clock verilog hdl source code, can be achieved when every minute of the time, you can adjust the time manually adjusting points.
Platform: | Size: 373760 | Author: 朱枫 | Hits:

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list

[VHDL-FPGA-Verilog] Verilog_Development_Board_Sources

[MPI] clock

[VHDL-FPGA-Verilog] clock_design

[VHDL-FPGA-Verilog] multifunction_digital_clock_based_on_fpga

[VHDL-FPGA-Verilog] multifunction_clock

[VHDL-FPGA-Verilog] dpll

[VHDL-FPGA-Verilog] clock

[VHDL-FPGA-Verilog] clock

[VHDL-FPGA-Verilog] digital-clock-

[VHDL-FPGA-Verilog] clock

[VHDL-FPGA-Verilog] Multifunction-digital-clock

[VHDL-FPGA-Verilog] clock

[VHDL-FPGA-Verilog] clock

[VHDL-FPGA-Verilog] digital-timer

[VHDL-FPGA-Verilog] muti-function-clock

[VHDL-FPGA-Verilog] shuzishizhong

[ELanguage] dIGITAL-CLOCK

[VHDL-FPGA-Verilog] clock

[VHDL-FPGA-Verilog] clock

[Software Engineering] Verilog-Code-For-Digital-Clock-Project

CodeBus www.codebus.net